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september 2013 doc id 022587 rev 2 1/46 1 l4969ur-e L4969URD-E system voltage regulator with fault tolerant low speed can transceiver features operating supply voltage 6 v to 28 v, transient up to 40 v low quiescent current consumption, less than 40 a in sleep mode two very low drop voltage regulators 5 v/200 ma separate voltage regulator for can transceiver supply with low power sleep mode efficient microcontroller supervision and reset logic 24 bit serial interface an unpowered or insufficiently supplied node does not disturb the bus lines v s voltage sense comparator supports transmission with groundshift: single wire 1.5 v - differential: 3 v description the l4969ur-e and L4969URD-E are integrated circuits containing 3 independent voltage regulators and a standard fault tolerant low speed can line interface in multipower bcd3s process. they integrate all main local functions for automotive body electronic applications connected to a can bus. powerso-20 so-20 table 1. device summary package order codes tube tape and reel so-20 L4969URD-E l4969urdtr-e powerso-20 l4969ur-e l4969urtr-e www.st.com
contents l4969ur-e, L4969URD-E 2/46 doc id 022587 rev 2 contents 1 block diagram and pins descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 v 1 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 v 2 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.3 v 3 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.4 internal supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 power-up, initialization and sleep mode transi tions . . . . . . . . . . . . . . . . . 17 3.3 can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 negligible errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 problematic errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.3 severe errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.4 wakeup via can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6.2 undervoltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6.3 reset signalling duri ng sleepmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 identifier filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 ground shift detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 serial interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 general dataframe format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.2 address/command field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.3 datafield #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.4 datafield #2/crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
l4969ur-e, L4969URD-E contents doc id 022587 rev 2 3/46 3.11 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 adr 0: vrcr voltage regulator control register . . . . . . . . . . . . . . . . . . . 28 4.2 adr 1: ctcr can - transceiver control register . . . . . . . . . . . . . . . . . . . 29 4.3 adr 2: gptr global parameter and test register . . . . . . . . . . . . . . . . . . 30 4.4 adr 3: rcadj rc-oscillator adjust register . . . . . . . . . . . . . . . . . . . . . . 30 4.5 adr4: wdc watchdog control register . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5.1 watchdog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5.2 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5.3 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5.4 wakeup watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 adr5: gien global interrupt enable register . . . . . . . . . . . . . . . . . . . . . . 35 4.7 adr6: ifr interrupt flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8 adr7: ctsr can transceiver status register . . . . . . . . . . . . . . . . . . . . . 36 4.9 adr 8 and 9: id01, id23 identifier filter sequence select register . . . . . . 37 4.10 adr 10: btl identifier filter bittimelogic control register . . . . . . . . . . . . . 38 4.11 adr 15: sys system status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 remarks for application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 so-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 powerso-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables l4969ur-e, L4969URD-E 4/46 doc id 022587 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data of powerso-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. voltage regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. voltage regulator 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. reset and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. can line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 11. serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. digital i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 12. diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 13. can error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 14. wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 15. operating mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 16. detectable physical busline failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 17. l4969ur memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. operating modes of the can line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. so-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. powerso-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
l4969ur-e, L4969URD-E list of figures doc id 022587 rev 2 5/46 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. wakeup signalling via rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5. nres pin internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6. nres timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. internal circuitry and suggested c ext for nres generation during sleep mode . . . . . . . . 23 figure 8. general dataframe format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. address / command field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. datafield #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. datafield #2 / crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. adr 0: vrcr voltage regulator control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. adr 1: ctcr can - transceiver control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. adr 2: gptr global parameter and test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. state transition duri ng oscillator calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16. state transition duri ng oscillator calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. adr4: wdc watchdog control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. watchdog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. window watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. wakeup watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 22. valid timing windows for wdc register rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 23. adr5: gien global interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. adr6: ifr interrupt flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 25. adr7: ctsr can transceiver status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 26. adr 8 and 9: id01, id23 identifier filter sequence select register . . . . . . . . . . . . . . . . . . . 37 figure 27. adr 10: btl identifier filter bittimelogic control register. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 28. adr 15: sys system status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29. interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 30. general circuit connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 31. so-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 32. powerso-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
block diagram and pins description l4969ur-e, L4969URD-E 6/46 doc id 022587 rev 2 1 block diagram and pins description figure 1. block diagram table 2. pins description pin number pin name function powerso-20 so-20 1, 10, 11, 20 5, 6, 15, 16 gnd power ground 2 7 v1 microcontroller supply voltage 3 8 v2 peripheral supply voltage 4 9 v3 internal can supply 5 10 vs power supply 6 11 canh canh line driver output 7 12 rtl canl termination source 8 13 canl canl line driver output 9 14 rth canh termination source 12 17 rxd act. low can receive dominant data output 13 18 txd act. low can transmit dominant data input 14 19 sout serial data output vreg 1 vreg 2 vreg 3 fault tolerant low speed can-transceiver 24 bit spi control and status memory identifier filter watchdog and adjustable rc-oscillator vs v1 v2 v3 canh canl rth rtl tx rx sclk sin sout wake nint nreset
l4969ur-e, L4969URD-E block diagram and pins description doc id 022587 rev 2 7/46 figure 2. pins configuration 15 20 sin serial data input 16 1 sclk serial clock 17 2 nres act. low reset output 18 3 nint act. low interrupt request 19 4 wake dual edge triggerable wakeup input table 2. pins description (continued) pin number pin name function powerso-20 so-20 nint wake gnd gnd v1 v2 v3 vs canh rtl canl rth rx gnd gnd tx sout sin sclk nres L4969URD-E so-20 gnd v1 v2 v3 vs canh rtl canl rth gnd gnd wake nint nres sclk sin sout txd rxd gnd l4969ur-e powerso-20
electrical specifications l4969ur-e, L4969URD-E 8/46 doc id 022587 rev 2 2 electrical specifications 2.1 absolute maximum ratings applying stress which exceeds the ratings listed in the table 3: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im plied. exposure to the conditions in this section for extended periods may affect device reliability. 2.2 thermal data table 3. absolute maximum ratings (1) 1. all pins of the ic are protected against esd. the ve rification is performed according to mil 883c, human body model with r = 1.5 k ? , c = 100 pf and discharge voltage 2000 v, corresponding to a maximum discharge energy of 0.2 mj. symbol parameter value unit v vsdc dc operating supply voltage -0.3 to 28 v v vstr transient operating supply vo ltage (t < 400 ms) -0.3 to 40 v i vout1...3 output currents internally limited t stg storage temperature -65 to 150 c t j operating junction temperature -40 to 150 c v out1 (2) 2. voltage forced means voltage limited to the specif ied values while the current is not limited. externally forced output voltage out1 -0.3 to v s + 0.3, max + 6.3 v v out2 (2) externally forced output voltage out2 -0.3 to v s + 0.3 v v out3 (2) externally forced output voltage out3 -0.3 to v s + 0.3, max + 6.3 v v inli input voltage logic inputs: sin, sclk, nres -0.3 to 7 v v inliw input voltage wake -0.3 to v s + 0.3 v v canh voltage canh line (3) 3. esd pulses on can-pins up to 4 kv hb m vs gnd with all other pins grounded. -28 to 40 v v canl voltage canl line -28 to 40 v table 4. thermal data of powerso-20 symbol parameter value unit r thj-a thermal resistance junction-ambient 40 (1) 1. typical value soldered on a pc board with 8 cm 2 copper ground plane (35m thick). c/w r thj-c thermal resistance junction-case 3 c/w
l4969ur-e, L4969URD-E electrical specifications doc id 022587 rev 2 9/46 2.3 electrical characteristics v s =14v, t j = -40c to 150c, unless otherwise specified table 5. supply current symbol parameter test conditions min. typ. max. unit i ssl all regulators off (canh standby timer off (sleep #1) 20 40 60 a timer on (sleep #2) 50 90 135 a i sslwk v 1 off, v 2 off, v 3 on (can rx only) rx only 2 4 6 ma i ssb v 1 only (can standby) timer off (standby #1) 100 150 250 a timer on (standby #2) 150 200 300 a default (standby #3) 350 440 600 a i s all regulators on, (can active, tx high) i out1 =-100ma; i out2 = -10 ma; no can load 110 120 150 ma i scp additional oscillator and charge pump current at low v s v s = 6 v; timer off 55 80 100 a v s = 6 v; timer on 10 30 50 a table 6. voltage regulator 1 symbol parameter test conditions min. typ. max. unit v 01 v 1 output voltage 6v-100ma (1) 1. valid for so-20 package 4.9 5 5.1 v 6v-150ma (2) 2. valid for powerso-20 package 4.9 5 5.1 v v dp1 dropout voltage 1@ v s =4.8v i out1 = -10 ma 0.0 0.025 0.06 v i out1 = -100 ma (1) 0.0 0.25 0.6 v i out1 = -150 ma (2) 0.0 0.4 0.9 v v ol01 load regulation 1 i o = -1 ma to -100 ma (1) 01040mv i o = -1 ma to -150 ma (2) 01040mv i lim1 current limit 1 0.8 v < v o1 <4.5v; v s =6v (1) -180 -400 -800 ma 0.8 v < v o1 <4.5v; v s =14v (2) -180 -400 -800 ma v oli1 line regulation 1 6 v < v s <28v; i o1 =-1ma 0 5 30 mv t ovt1 overtemp flag 1 6 v < v s < 28 v 130 140 150 c t otkl1 thermal shutdown 1 6 v < v s < 28 v 175 185 205 c v res min v 1 reset threshold voltage rtc0 = 0 4.15 4.5 4.7 v rtc0 = 1 3.7 4.0 4.2 v
electrical specifications l4969ur-e, L4969URD-E 10/46 doc id 022587 rev 2 table 7. voltage regulator 2 and 3 symbol parameter test cond itions min. typ. max. unit v o output voltage 6v-100ma (1) 1. valid for so-20 package 4.8 5 5.2 v 6v-150ma (2) 2. valid for powerso-20 package 4.8 5 5.2 v v dp dropout voltage v s = 4.8 v; i out =100ma (1) 0.0 0.25 0.6 v i out =150ma (2) 0.0 0.4 0.9 v v olo load regulation i o = -1 ma to -100 ma (1) 01040mv i o = -1 ma to -150 ma (2) 01040mv i lim current limit 0.8 v < v o1 < 4.5 v; v s =6v (1) -180 -400 -800 ma 0.8 v < v o1 <4.5v (2) -180 -400 -800 ma v oli line regulation 6 v < v s <28v; i out =- 5ma 0 5 30 mv t ovt overtemp flag 6 v < v s < 28 v 130 140 150 c t otkl thermal shutdown 6 v < v s < 28 v 150 165 180 c vtrc v 2 tracking offset 6 v < v s <28v; i o2 =0 -90 0 +90 mv table 8. reset and watchdog symbol parameter test conditions min. typ. max. unit t osc onchip rc-timebase rc-adjustment = 0 normal, rxonly, standby3 (?1mhz?) 0.95 1.1 1.35 s t oscslow sleep2, standby2 (?250khz?) 4.0 5.4 6.8 s t wdc watchdog timebase (2.5 ms) normal, rxonly, standby3 (?1mhz?) 2498 t osc sleep2, standby2 (?250khz?) 624 t oscslow t rdnom reset pulse duration (1 ms) 1024 t osc t wdstart reset pulse pause (320 ms) (startup watchdog) 128 t wdc t wdsws watchdog window start (software window watchdog) swt = 0 (2.5 ms) 1 t wdc swt = 1 (5 ms) 2 t wdc swt = 2 (10 ms) 4 t wdc swt = 3 (20 ms) 8 t wdc t wdswe watchdog window end (software window watchdog) swt = 0 (5 ms) 2 t wdc swt = 1 (10 ms) 4 t wdc swt = 2 (20 ms) 8 t wdc swt = 3 (40 ms) 16 t wdc
l4969ur-e, L4969URD-E electrical specifications doc id 022587 rev 2 11/46 t wd1c system watchdog 1 wdt = 0 (80 ms) 32 t wdc wdt = 1 (160 ms) 64 t wdc wdt = 2 (320 ms) 128 t wdc wdt = 3 (640 ms) 256 t wdc wdt = 4 (800 ms) 320 t wdc t wd2c system watchdog 2 wdt = 8 (1 s) 400 t wdc wdt = 9 (2 s) 784 t wdc wdt = 10 (4 s) 1600 t wdc wdt = 11 (8 s) 3200 t wdc wdt = 12 (45 min) 1081344 t wdc v resl reset output low voltage i res = 500 a; v 1 =2.5v 00.30.4 v i res = 500 a; v 1 =1.5v 00.851.4 v r pures internal reset pull-up resistance 80 120 280 k ? table 9. can line interface symbol parameter test conditions min. typ. max. unit t drd propagation delay (rec to dom state) c load = 3.3 nf 0.4 1.0 1.5 s t ddr propagation delay (dom to rez state) c load =3.3nf; r term = 100 ? 0.4 1.0 2.0 s s rd bus output slew rate (r ? d) 10% ... 90%; c load =3.3nf 458v/s r rth , r rtl external termination resistance (application limit) 0.5 16 k ? v ccfs force standby mode (fail safe) min v s to turn off can- if and v 3 2.20 4.0 v vh rxd high level output voltage on rxd v 1 - 0.9 v 1 v vl rxd low level output voltage on rxd 00.9v vd_r differential receiver dom to rec threshold v canh - v canl no bus failures -3.85 -2.50 v vr_d differential receiver rez to dom threshold v canh - v canl no bus failures -3.50 -2.20 v v canhr canh recessive output voltage txd = v 1 ; r rth <4k 0.35 v table 8. reset and watchdog (continued) symbol parameter test conditions min. typ. max. unit
electrical specifications l4969ur-e, L4969URD-E 12/46 doc id 022587 rev 2 v canhd canh dominant output voltage txd = 0; i canh =40ma v 3 - 1.4 v v v canlr canl recessive output voltage txd = v 1 ; r rtl <4k v 3 - 0.2 v v v canld canl dominant output voltage txd = 0; i canl =-40ma 1.4 v i canh canh dominant output current txd = 0; v canh = 0 v 70 100 160 ma i canl canl dominant output current txd = 0; v canl =14v -70 -100 -160 ma i lcanh canh sleep mode leakage current sleep mode. t j =150c ; v canh =0v -10 0 -10 a i lcanl canl sleep mode leakage current sleep mode. t j =150c ; v canl =0v; v s =12v -10 0 -10 a v wakeh canh wakeup voltage sleep/ standby mode 1.2 1.9 2.7 v v wakel canl wakeup voltage sleep/ standby mode 2.4 3.1 3.8 v v canhs canh single ended receiver threshold normal mode. -5 v < canl < v s 1.5 1.82 2.15 v v canls canl single ended receiver threshold normal mode. -5 v < canh < v s 2.7 3.1 3.4 v v ovh canh overvoltage detection threshold normal mode. -5 v < canl < v s 6.5 7.2 8.0 v v ovl canl overvoltage detection threshold normal mode. -5 v < canh < v s 6.5 7.2 8.0 v rt rth internal rth to gnd termination resistance normal mode, no failures. v rth =1v 25 45 80 ? it rthf internal rth to gnd termination current normal mode, failure eiii v rth =v 3 - 1 v 55 75 100 a rt rtl internal rtl to v cc termination resistance normal mode, no failures. v rtl =v 3 - 1 v 25 45 85 ? it rtlf internal rtl to v cc termination current normal mode. (failure eiv, evi, evii) v rtl =v 3 - 1 v -6 -40 -70 a rt rtls internal rtl to v s termination resistance. no failures. standby/sleep mode. v rtl =1v, 4v 71326k ? table 9. can line in terface (continued) symbol parameter test conditions min. typ. max. unit
l4969ur-e, L4969URD-E electrical specifications doc id 022587 rev 2 13/46 table 10. digital i/o symbol parameter test conditions min. typ. max. unit v sinl low level input voltage 0 0.9 v v sinh high level input voltage v 1 - 0.9 v 1 v v sclkl low level input voltage 0 0.9 v v sclkh high level input voltage v 1 - 0.9 v 1 v v txl low level input voltage 0 0.9 v v txh high level input voltage v 1 - 0.9 v 1 v v wakel low level input voltage 0 0.9 v v wakeh high level input voltage 4.1 5.0 v v south high level output voltage v 1 - 0.9 v 1 v v soutl low level output voltage 0 0.9 v v rxdh high level output voltage v 1 - 0.9 v 1 v v rxdl low level output voltage 0 0.9 v ioh rxd high level output current rxd = 0 -2.5 -1.8 -0.9 ma iol rxd low level output current rxd = 5 v 0.9 1.6 2.5 ma ioh sout high level output current sout = 0 -18.0 -14.0 -7.0 ma iol sout low level output current sout = 5 v 15 24 35 ma ioh int high level output current int = 0 -20 -15 -8 ma iol int low level output current int = 5 v 15 24 35 ma ioh reset high level output current reset = 0 -25.0 -15,0 -6.0 a iol reset low level output current reset = 5 v 5.0 7.5 10.0 ma ioh wake high level output current v wake = 5 v -1.5 0 1.5 a iol wake low level output current v wake = 0 v -4.5 -3.4 -2.0 a table 11. serial data interface symbol parameter test conditions min. typ. max. unit t start sin low to sclk low setup time (frame start) 100 ns t setup sin to sclk setup time (write) 100 ns t hold sin to sclk hold time (write) 100 ns t d sclk to sout delay time (read) 500 ns t ckmax sclk maximum cycle time (timeout) 11.53.0ms t gap interframe gap 5 s f sclk sclk frequency range 0.25 0.5 1 mhz
electrical specifications l4969ur-e, L4969URD-E 14/46 doc id 022587 rev 2 table 12. diagnostic functions symbol parameter test cond itions min. typ. max. unit vs min sense comparator detection threshold 6.0 7.2 8,0 v gs canh canh groundshift detection threshold -1.5 -1 -0.6 v table 13. can error detection symbol parameter test conditions min. typ. max. unit n edgeh nr of dom to rec edges on canl to detect permanent rez canh operating mode (ei_v) 3 edges n edgehr nr of dom to rec edges to detect recovery of canh operating mode (ei_v) 3 edges n edgel nr of dom to rec edges on canh to detect permanent rez canl operating mode (eii_ix) 3 edges n edgelr nr of dom to rec edges to detect recovery of canl operating mode (eii_ix) 3 edges t eiii canh to v s short circuit detection time operating mode (eiii) 1.6 2 3.6 ms sleep/ standby mode (eiii) 1.6 2 3.6 ms t eiiir canh to v s short circuit recovery time operating mode (eiii) 0.4 0.9 1.6 ms sleep/ standby mode (eiii) 0.4 0.9 1.6 ms t eiv canl to gnd short circuit detection time operating mode (eiv) 0.4 0.9 1.6 ms sleep/ standby mode (eiv) 0.4 0.9 1.6 ms t eivr canl to gnd short circuit recovery time operating mode (eiv) 10 30 50 s sleep/ standby mode (eiv) 0.4 0.9 1.6 ms t evi canl to v s short circuit detection time operating mode (evi) 0.4 0.9 1.6 ms t evir canl to v s short circuit recovery time operating mode (evi) 200 500 750 s t evii canl to canh short circuit detection time operating mode (evii) 0.4 0.9 1.6 ms t eviir canl to canh short circuit recovery time operating mode (evii) 10 30 50 s t eviii canh to vdd short circuit detection time operating mode (eviii) 1.6 1.8 3.6 ms sleep/ standby mode (eviii) 1.6 1.8 3.6 ms t eviiir canh to vdd short circuit recovery time operating mode (eviii) 0.4 0.9 1.6 ms sleep/ standby mode (eviii) 0.4 0.9 1.6 ms
l4969ur-e, L4969URD-E electrical specifications doc id 022587 rev 2 15/46 t failtx tx permanent dominant detection time (fail safe) operating mode (ex) 0.4 0.9 1.6 ms t failtxr tx permanent dominant recovery time (fail safe) operating mode (ex) 1 4 8 s table 14. wakeup symbol parameter test conditions min. typ. max. unit t wucan minimum dominant time for wake-up via canh or canl sleep/standby 8 22 38 s t wuwk minimum pulse time for wake- up via wake sleep/standby 8 22 38 s table 13. can error de tection (c ontinued) symbol parameter test conditions min. typ. max. unit
functional description l4969ur-e, L4969URD-E 16/46 doc id 022587 rev 2 3 functional description 3.1 general features the l4969ur is a monolithic integrated circuit which provides all main functions for an automotive body can network. it features two independent regulated voltage supplies v 1 and v 2 , an interrupt and reset logic with internal clock generator, serial interface and a low speed can-bus transceiver which is supplied by a separate third voltage regulator (v 3 ). the device guarantees a clearly defined behavior in case of failure, to avoid permanent can bus errors. the device operates in four basic modes, with additional programming for v 1 standby modes in ctcr: 3.1.1 v 1 output voltage the v 1 regulator uses a dmos transistor as an ou tput stage. with this structure very low dropout voltage is obtained. the dropout operation of the standby regulator is maintained down to 4 v input supply voltage. the output voltage is regulated up to the transient input supply voltage of 40 v. with this feature no functional interruption due to overvoltage pulses is generated. the output 1 regulator is switched off in sleep mode. 3.1.2 v 2 output voltage the v 2 regulator uses the same output structure as the output 1 regulator except to being short circuit proof to v s . the v 2 output can be switched on and off through a dedicated enable bit in the control register. in addition a tracking option can be enabled to allow v 2 follow v 1 with constant offset. this feature allows consistent a/d conversion inside the microcontroller (supplied by v 1 ) when the converted signals are referenced to v 2 . the maximum voltage that can be applied to v 2 is v s + 0.3 v up to a max v s of 40 v. table 15. operating mode description mode v1 v2 v3 timer/wdc can-if i typ lp1, lp0 (ctcr) remarks sleep #1 off off off off standby 40 x,x no timer based wakeup sleep #2 off off off on (250khz) standby 80 x,x timer active based on t oscslow standby #1 (1) on off off off standby 170 1,1 no watchdog or timer standby #2 (1) on off off on (250khz) standby 210 1,0 watchdog or timer active based on t oscslow standby #3 on off off on (1mhz) standby 440 0,0 watchdog or timer activ, por default rxonly off off on on (1mhz) rx-only 4ma x,x active during busactivity to filter id, auto- matic fall back to sleep when bus idle normal on on on on (1mhz) normal 5ma x,x no currents from can or regulators 1. note, that in order to enter either standby #1 or standby #2 the startup-watchdog has to be acknowledged, in standby #1, the window watchdog has to be disabled as descri bed in chapter 2.5, to allow the decativation of the internal oscillator.
l4969ur-e, L4969URD-E functional description doc id 022587 rev 2 17/46 3.1.3 v 3 output voltage the third voltage regulator of the device generates the supply voltage for the internal logic and the can-transceiver. in operating mode it is capable of supplying up to 200 ma in order to guarantee the required short circuit current for the can_h driver. the sleep and operating modes are switched through a dedicated enable bit. 3.1.4 internal supply voltage a low power sleep mode regulator supplies the internal logic in sleep mode. 3.2 power-up, initialization and sleep mode transitions the following state-diagram illustrates the poss ible mode transitions inside the device. as a prerequisite, an spi-connection to the microcontroller with the correct crc-algorythms is required. during the debug phase the nres line can be forced high externally (connect to v 1 ) to deactivate the startup failure mechanism and keeping v 1 alive.
functional description l4969ur-e, L4969URD-E 18/46 doc id 022587 rev 2 figure 3. state diagram 3.3 can transceiver ? supports double wire unshielded busses ? baud rate up to 125 kbaud ? short circuit protection (battery, ground, wires shorted) ? single wire operation possible (automatic switching to single wire upon bus failures) ? bus not loaded in case of unpowered transceiver the can transceiver stage is able to transfer serial data on two independent communication wires either deferentially (normal operation) or in case of a single wire fault on the remaining line. the physical bitcoding is done using dominant (transmitter active) and overwritable startup v1 active v2, v3, can off t=320ms startup failure t=1ms (fail ++) fail = 7 forced sleep wakeup v1 off v1 low reset low wdc-ack wdc-ack window watchdog refresh t=t win2 wdc-ok wdc-fail normal mode window wdc active wnd set normal mode window wdc disabled timer active wden set timeout | (wdc-ack & not timeout (1) ) nres low programmed disar set disar set wakeup wakeup&v1_uv writing to the wdc- register (wdc-ack) the normal state is entered. a missing ack within 320ms will initiate a startup failure phase (reset low). if no wdc-ack is received within seven retrials the voltage regulator v1 will be turned off by entering the forced sleep state. depending on the value from the last wdc-ack, another one has to be written within the specified time frame (swdc[1:0]). a failure will activate the startup state the window supervision can temporarily be de- activated for the time programmed during the last wdc-ack (wdt[3:0]). upon rewriting (wdc-ack) or expiry of the timer, the normal state is reentered. if during the last wdc-ack wnd has been set (after releasing write lock, see description of watchdog control register) the win- dow watchdog is deactivated, and no uc supervision is active. timer active wden set (restart by double wdc-ack & wden) timeout | wdc-ack here the timer can be used to generate time events (i.e. wake-up uc from stop) after por, v1 up or externally forced reset through low nres, the startup state is entered the forced sleep mode is left upon wake-up through either can or edge on wake. applying a permanent wake-up (i.e. both can-lines dominant) pre- vents v1 from being turned off (can be used during system debugging) setting disar (see voltage regulator control register) voltage regulator v1 is turned off, and the output voltage is decreasing depending on the external load and blocking capacitor. note, that during this transition no reset will be generated (due to debug mode). upon wake-up howewer nres will be pulled low, if v1was below the programma- ble reset threshold (v1_uv). forcing nres high externally, fail will not be incremented (emulation) (restart by double wdc-ack & wden) wakeup wdc-ack wden set & sleep v1 off no reset wakeup &v1_uv no reset (1) rewriting of the wdc register when the timer just expires can lead to an unwanted window watchdog failure resulting in a low pulse on reset (see note on section 4.5.4)
l4969ur-e, L4969URD-E functional description doc id 022587 rev 2 19/46 recessive states. too long dominant phases are detected internally and further transmission is automatically disabled (malfunction of prot ocol unit does not affect communication on the bus, "fail-safe" - mechanism). for low curren t consumption during bus inactivity a sleep mode is available. the operating mode can be entered from the sleep mode either by local wake up (microcontroller) or upon detection of a dominant bit on the can-bus (external wake up). ten different errors on the physical buslines can be distinguished: note: not all of the 10 different errors lead to a breakdown of the whole communication. so the errors can be categorized into 'negligible', 'problematic' and 'severe': 3.3.1 negligible errors transmitter ? error i and ii (canh or canl interrupted but still tied to termination) ? error iv and viii (canh or canl permanently dominant by short circuit) in all cases above data can still be transmitted in differential mode. receiver ? error i and ii (canh or canl interrupted but still tied to termination). ? error v and ix (canh or canl permanently recessive by short circuit). in all cases above data can still be received in differential mode. table 16. detectable physical busline failures n type of errors conditions errors caused by damage of the datalines or isolation i canh wire interrupted (tied to ground or termination) edgecount difference > 3 ii canl wire interrupted (floating or tied terminationk) edgecount difference > 3 iii canh short circuit to v bat (overvoltage condition) v(canh) > 7.2 v after 3.6 ms iv canl short circuit to gnd (permanently dominant) v(canl) < 3.1 v & v(canh)-v(canl) > -3.25 v after 1.6 ms v canh short circuit to gnd (permanent ly recessive) edgecount difference > 3 vi canl short circuit to v bat (overvoltage condition) v(canl) > 7.2 v after 1.6 ms vii canl shorted to canh v(canh) - v(canl) < -3.25 v after 1.6 ms errors caused by misbehav ior of transceiver stage viii canh short circuit to vdd (permanently dominant) v(canh) > 1.8 v & v(canh) - v(canl) > -3.25 v after 3.2 ms ix canl short circuit to vdd (permanently recessive) edgecount difference > 3 errors caused by defective protocol unit x canh, canl driven dominant for more than 1.6 ms
functional description l4969ur-e, L4969URD-E 20/46 doc id 022587 rev 2 3.3.2 problematic errors transmitter ? error iii and vi (canh or canl show overvoltage condition by short circuit). data is transmitted using the re maining dataline (single wire). receiver ? error iii and vi (canh or canl show overvoltage condition by short circuit). data is received using the re maining dataline (single wire). 3.3.3 severe errors transmitter ? error v and ix (canh or canl permanently recessive by short circuit). data is transmitted on the remaining dataline after short circuit detection. ? error vii (canh is shorted to canl). data is transmitted on canh or canl after overcurrent was detected. ? error x (attempt to transmit more than 10 successive dominant bits (at lowest bitrate specified). transmission is terminated (fail safe). receiver ? error vii (canh is shorted to canl). data is received on canh or canl after detection of permanent dominant state. ? error iv and viii (canh or canl permanently dominant by short circuit). data is received on canh or canl after short circuit was detected. ? error x (reception of a sequence of domin ant bits, violating the protocol rules). data is received normally, error is detected by protocol-unit. the error conditions is signaled issuing an error flag inside a dedicated register which is readable by the microcontroller through the serial interface. the information of the error type (i through x) is also stored into this register. 3.3.4 wakeup via can when the can transceiver is in standby mode special low power comparators detect activity on canh and / or canl. this information is filtered and can be defined as a wakeup condition for the voltage regulator and the application via the ?wkc? flag in the ifr register as a maskable interrupt through nint or via rx. the wakeup signalling via rx is de scribed in the following diagram: figure 4. wakeup signalling via rx canx rx t wucan t osc < t wucan t wurep dominant recessive
l4969ur-e, L4969URD-E functional description doc id 022587 rev 2 21/46 after detecting a dominant level on either canh or canl for longer than the wakeup filter time (t wucan ), rx goes low for one t osc cycle. this is repeated cyclically every t wurep until canx returns to a recessive state or canx is considered as shorted to a dominant value. note, that the duration of the extended cycle t wurep equals t wucan when the oscillator is in 1 mhz mode (standby3, rxonly and normal mode, see ta b l e 1 5 ). if the device uses the low power oscillator (250 khz) in either sleep2 or standby2 t wurep = 4.2 x t wucan . 3.4 oscillator a low power oscillator provides an internal cl ock, that can be calibra ted in a range from -16% to +16% via the rcadj register using the c-xtal as a reference. in the operating modes sleep2 and standby2 (watchdog / timer active) the output frequency is ~250 khz (1/ t oscslow ), if the watchdog function is not requested, the internal oscillator is switched off. in the operating modes normal , rxonly and standby3 the oscillator is running at ~1 mhz (1/ t osc ). 3.5 watchdog a triple function programmable watchdog is integrated to perfo rm the following tasks: wakeup watchdog: when in sleep or standby mode the watchdog can generate a wakeup condition after a programmable period of time ranging from 80 ms up to 45 minutes startup watchdog: upon v 1 power-up or microcontroller failure during spi supervision a reset pulse is generated periodically every 320 ms for 2.5 ms until activity of the microcontroller is detected (spi sequence) or no acknowledg e is received within 7 cycles (2.2 sec). in this condition the device is forced into sleep mode until a wakeup is detected and a startup cycle is reinitialized. window watchdog: after passing the startup sequence, this watchdog request an acknowledge by the microcontroller via the spi within a programmable timing frame, ranging from 2.5 ... 5 ms up to 20 ... 40 ms. upon a missing or misplaced acknowledge the startup watchdog is initialized. 3.6 reset 3.6.1 power-on reset upon power-on (v s > 3.5 v), the internal reset forces the device into a predefined power-on state (see section 3.1: general features ): standby #3: v 1 on v 2 off v 3 off,can-standby mode, id-filter disabled, startup watchdog active.
functional description l4969ur-e, L4969URD-E 22/46 doc id 022587 rev 2 with v s below 5 v the regulator v 1 will follow v s with minimum drop. the microcontroller retrieves a reset if v 1 is dropping below a programmable voltage level of either 4.5v (default) or 4.0 v. the programmed state of the l4969ur remains unchanged. the act. low reset pulse duration is fixed internally by an open-drain output stage to 1 ms. however, this time can be externally extended by an addition al capacitance connect between nreset and ground which is then charged by the internal pull-up of typical 120 k. depending on the reset-input-threshold of the microcontroller (u tr ), the required capacitance for a typical t d can be calculated as follows: c ext = -t d / (120e3 ln(1-u tr /v 1 )). to obtain a reset-pulse duration of t d = 50 ms with u tr /v 1 = 0.5, a capacitance of c ext = -50e-3 / (120e3 ln 0.5) = 600 nf is required figure 5. nres pin internal structure 3.6.2 undervoltage reset upon detection of a v 1 voltage level below a programmable voltage level of either 4.5 v (default) or 4.0 v, the nres-pin is pulled low. since this undervoltage detection is additionally sampled periodically every ms, the nres low time will be extended by up to 1ms if v 1 was low (v 1uv ) at the sampling point (see figure 6 ). figure 6. nres timings 3.6.3 reset signal ling during sleepmode when entering the sleep mode by writing 1 to disar in the vrcr register, the voltage regulators and their references will be deactivated to allow minimum current consumption. by removing the v 1 reference, the output voltage is no longer supervised and thus no reset will be generated. now two scenarios are possible (see figure 3: state diagram ): 1) wakeup with v 1 still above reset threshold: v 1 will be reactivated and normal mode is resumed 2) wakeup with v 1 below reset threshold: v 1 will be activated, nres will go low and remain low until v 1 is above reset threshold and startup mode is entered. v1 120k nres c ext to reset input of uc 1ms sampling v1 uv nres
l4969ur-e, L4969URD-E functional description doc id 022587 rev 2 23/46 the scenario 2 is the most critical when used with microcontroller that do not have their own por circuitry. in this case v 1 will ramp down with an un known application state. to guarantee a proper shut off of a microcontroller without an internal por circuitry the following mechanism can be utilized: the l4969ur uses a bidirectional reset to detect a possible watchdog failure of the microcontrolle r. if this failure condition is detected, nres will be forced low for 1 ms (with activated timer) or until a wakeup c ondition occurs (wden bit in wdc register reset, thus rc-oscilla tor will be switched off during sleep). two methods can be used to allow a proper sleep transition: with timer (wden = 1): immediately after setting disar the microcontroller has to program its wdc to generate a failure causing the l4969ur to detect a low level on nres followed by an automatic 1 ms pulse extension. if v 1 is ramping down slow, cext has to be defined in a way, that nres will stay below the input threshold of the microcontroller until v 1 is in a safe level. without timer (wden = 0): same procedure as above, but microcontroller has to generate a reset within 1 ms after wden has been cleared. nres will then stay low, until a wakeup condition occurs. figure 7. internal circuitry and suggested c ext for nres generation during sleep mode 3.7 identifier filter a 12-bit can-id-filter is im plemented allowing wakeup via specific can-messages thus aiding the implementation of low power partial communication networks like standby diagnostics without the need to power-up the whole network. to guarantee the detection of the programmed identifiers, the local rc-oscillator can be calibrated to allow the programmable bittime logic to extract the incoming stream with a maximum of tolerance over temperature deviation. 3.8 ground shift detection in case of single wire communication via canh the signal to noise ratio is low. detecting the local ground shift can be used as an additional indicator on the current signal quality. the v1 nres c ext disar ref reg 1ms rc-osc r1 r2 wdc l4969ur c
functional description l4969ur-e, L4969URD-E 24/46 doc id 022587 rev 2 information of the integrated ground shift detector will be re freshed upon ever y falling edge on tx and can be read from the can transceiver status register (ctsr). it will be set, if v(canh) < -1 v, reset if v(canh > -1 v) at the falling edge of tx. 3.9 thermal protection the device features three independent thermal warning circuits which monitor the temperature of the v 1 output, the v 2 output and the can_h and can_l drivers together with voltage regulator v 3 . each circuit sets a separate overtemperature flag in a register which is read and writable by the serial in terface. the overtemperature flags cause an interrupt to the microcontroller. the microcontroller is able to switch v 1 , v 2 and can drivers on and off through dedicated enable registers. to enhance system security the following strategy is chosen for thermal warning and shutdown: 3 independent warning flags are set at 140c for v 1 , v 2 and v 3 /can-transceiver at 170c v 2 and v 3 switched off at 200c v 1 is switched off v 2 and v 3 can be switched on again through the microcontroller v 1 can be switched on again at wake-up (watchdog wake-up, can wake-up, external wake-up) note, that if no wakeup source is set for v 1 the external wake pin and the can interface will be activated to allow a proper retry cycle. 3.10 serial interface (spi) a standard serial peripheral interface (spi) is implemented to allow access to the internal registers of the l4969ur. a total of 12 registers with different datalengths can be directly read from or written to, providing the requested address at the beginning of a dataframe. upon every access to this interface, the content of the register currently accessed is shifted out via sout. all operations are performed on the rising edge of sclk. if a frame is not completed, the interface is automatically reset after 1.5 ms of sclk idle time (auto timeout detection). if a message is corrupted (additional or missing sclk pulses), the application software can detect this by evaluating the returned value of the crc and force a communication gap of min 1.5 ms to allow communication recovery. a corruption can be caused during startup of the microcontroller and spi initialization. the application should then wait at least 1.5 ms after spi init prior to starting the communication. the dataframe format used is described on section 3.10.1: general dataframe format .
l4969ur-e, L4969URD-E functional description doc id 022587 rev 2 25/46 3.10.1 general dataframe format figure 8. general dataframe format data is sampled on the rising edge of the clock and sout will change upon sclk falling. sout will show a copy of sin for the address/ command field for initial data path checks. independently of the command st ate, sout will show the conten t of the register addressed. sin contains either data to be written or arbitrary data for all other operations. the transaction will be terminated with four bit of data followed by a 4-bit wide crc (cyclic redundancy check) as a result of either sin related data or calculated automatically on data returned via sout. here the microcontroller has to provide the correct sequence in order to get the write command activated insi de. a crc-failure is signalled via nint. for returned data the crc can also be used to verify a successful transfer. note: the information in data field 1 is copied from the adressed register into the spi shift register at the last rising sclk edge of the address/command field. a clear or write operation on the addressed register takes place after the last (24th) rising sclk edge of the telegram if the crc check passes. as a consequence any read/clear or write spi command can remove the information from the addressed register that was set after the register content has been copied into the shift register for reading. this has to be considered especially in interrupt service routines processing wakeup watchdog restarts that need to be synchronized with the ?wkw? flag inside the ifr register. 3.10.2 address/command field figure 9. address / command field adr2 adr1 adr3 1 0 adr0 c1 c0 70 frame start sequence always has to be transmitted as 0 1 address field specifying the control/status word to be accessed spi command: 00: read register 01: clear ifr 10: illegal command 11: write register
functional description l4969ur-e, L4969URD-E 26/46 doc id 022587 rev 2 the address/command field starts with a 2-bit start sequence consisting of ?01?. any other sequence will lead to a protocol error signalled via the nint. t he address field is specifying the register to be accessed. the spi command flags allow in addition to the normal read/write operation to clear the interrupt flag register after read. 3.10.3 datafield #1 figure 10. datafield #1 datafield #1 contains either the lower 8 bits of a 12-bit frame or the complete byte of an 8-bit transfer. note, that sout is always showing the content of the register currently accessed and not a copy of sin as during the address/command field. 3.10.4 datafield #2/crc figure 11. datafield #2 / crc datafield #2 contains either the upper four bits of a 12-bit frame or zeros in case of an 8-bit transfer. this field is followed by a four bit crc sequence that is calculated based upon the polynom 0x11h (17 decimal). this sequence is simply the remainder of a polynomial division performed on the data previously transferred. if the crc appended to the sin sequence fails, any writing will be disabled and an error is signalled via nint. another remainder is calculated on the sout stream and appended accordingly to allow the application software to validate the correctness of incoming data. to aid evaluation, the crc checking can be turned off by writing arbitrary data with a valid crc to address 15. crc- checking will be reenabled upon another operation of this kind (toggled information).
l4969ur-e, L4969URD-E functional description doc id 022587 rev 2 27/46 3.11 memory map the memory space is divided up into 16 differ ent registers each being directly accessible using the spi. each register contains specific information of a functional group. in general all reserved bitpositions (?res?) have to be written with ?0?. undefined bits are read as ?0? and cannot be overwritten. in addition there is one register (ctsr) being read only, thus any wr ite attempt will leave the register content unchanged. certain interlock mechanisms exist to prevent unwanted overwriting of important functions i.e. voltage regulators or oscillator adjustments. these mechanisms are described with the functions of these registers. table 17. l4969ur memory map adr group msb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 vrcr undefined register memory euv3 euv2 rtc0 trc res env3 env2 disar 1 ctcr act txen res res ovr lp2 lp1 lp0 2 gptr res res res res tm1 tm0 tmux ten 3 rcadj cg1 cg0 pgen sign adj3 adj2 adj1 adj0 4 wdc wden wnd swt1 swt0 wdt3 wdt2 wdt1 wdt0 5 gien iset ires euv eovt eew ecw eww eifw 6 ifr espi iset ires uv23 uvvs ovt3 ovt2 ovt1 wke wkc wkw wkif 7 ctsr res res res gsh ex eviii evii evi eiv eiii eii ei 8 id01 a11 a10 a01 a00 b11 b10 b01 b00 c11 c10 c01 c00 9 id23 d11 d10 d01 d00 e11 e10 e01 e00 f11 f10 f01 f00 10 btl ps23 ps22 ps21 ps20 ps13 ps12 ps11 ps10 td3 td2 td1 td0 11 nav undefined register memory 12 nav 13 nav 14 test t11 t10 t09 t08 t07 t06 t05 t04 t03 t02 t01 t00 15 sys undefined register memory ncrc stat wndf stf otf ucf wake npor
control and status registers l4969ur-e, L4969URD-E 28/46 doc id 022587 rev 2 4 control and status registers the functionality of the device can be observed and controlled through a set of registers which are read and writable by the serial interface. 4.1 adr 0: vrcr voltage regulator control register figure 12. adr 0: vrcr voltag e regulator control register note, that when using the undervoltage-detection, euv2 and euv3 have to be activated after v 2 or v 3 have been turned on and settled (t > 1 ms). otherwise unwanted undervoltage can be detectected during turn on of the corresponding voltage regulator. trc disable all regulators (go to sleep) enable regulator #3. v3 will be activated by either setting env3 or upon enabling of the can lineinterface enable regulator #2. enable regulator #2 tracking option res to have v2 following v1 with constant offset rtc0 set reset threshold value to 4.0v default value is ?0? (4.5v) euv2 euv3 env3 env2 disar has to be default value is ?0? (disabled) default value is ?0? (disabled) this bit will be aut omatically reset upon overtemperature from canif or regulator #3 default value is ?0? (disabled) this bit will be aut omatically reset upon overtemperature at regulator #2. d7 d0 disar v1 v3 (disar & env3 | act) & tsdv3 trc v2 disar & env2 note, that at least one wake-up source to enable access. this bit will be automatically set upon the system failures overtemperature v1 enable undervoltage detection on regulator #2 and #3 ref (see note below) note , that due to the large initial char ging current of the output capacitors, the activation of v2 and v3 within the same command is not recommended written as ?0?. without a pending wake-up is required or watchdog startup failure. disar will be cleared upon a valid wake-up signal which is either defined in gien or is forced to wake or can after a system failure v3 will be activated upon vrcr.env3 or cctr.act without pending thermal shutdown note, that no reset will be generated from low v1 during sleep mode transition the reset line has to be forced low externally, or through a window failure also leaving env2 or env3 set when setting disar can therefore not be recommended (after wake-up v1 and v2 or v3 would be turned on)
l4969ur-e, L4969URD-E control and status registers doc id 022587 rev 2 29/46 4.2 adr 1: ctcr can - tr ansceiver control register figure 13. adr 1: ctcr can - transceiver control register three basic operating modes are available using different logic combinations on act and txen. each of these modes in conjunction with other inputs has its unique combination of parameters inside the specification: table 18. operating modes of the can line interface input signals output signals act txen tx canh canl v3 mode rtl rth canh canl rx 0 x x rth rtl on standby v bat gnd off off 1 101/0rthrtlonrxonlyv dd gnd off off tx 1 0 1 rtl on rxonly v dd gnd off off 1 0 1 rth on rxonly v dd gnd off off 111rthrtlonnormalv dd gnd on on 1 110rthrtlonnormalv dd gnd vdd gnd 0 111 rtlonnormalv dd gnd on on 111rth onnormalv dd gnd on on 110 *1 rth rtl on error x v dd gnd off off 1 1x1vdd *1 rtl on error vii, viii v dd isrc off on canl 1x1vs *1 rtl on error eiii, vii, viii v dd isrc off on canl 1 x 1 gnd x 3 on error ei_v v dd gnd on on 1x1 x 3v dd on error eii_ix v dd gnd on on 1x1rthvs *1 on error evi isrc gnd on off canh res txen act res ovr lp2 reserved bits (?res?) have to be written as ?0?. can-transceiver application control 0x: standby / sleep 10: receive only mode a (readback tx, if not ex) 11: normal operation d7 d0 note, that txen is automatically reset upon occurrence of ex (tx permanent dominant) and has to be reprogrammed after problem correction to enter normal mode. lp1 lp0 standby-mode control (v1 only, see 1.1) enable auto-osc-off reduce osc-frequency to 250khz canl over voltage retry threshold default value is ?0?, threshold is 7.2v set to ?1?, threshold is 3.2v note: if canl ov is detected, the programmed threshold is used to validate if transmission on canl is valid and can be continued.
control and status registers l4969ur-e, L4969URD-E 30/46 doc id 022587 rev 2 4.3 adr 2: gptr global pa rameter and test register figure 14. adr 2: gptr global parameter and test register note: this register is to be used for test purpose only, all bits have to remain ?zero? 4.4 adr 3: rcadj rc-osc illator adjust register figure 15. state transition during oscillator calibration during normal operation the microcontroller c an set cg1 and cg0 to ?01? to force a 200hz rectangular waveform on nint with 50% duty cycl e. note, that all other pending interrupts have to be cleared before. 1x1rthgnd *1 on error evii, eiv isrc gnd on off canh 1x1canl *1 canh *1 on error evii isrc gnd on off canh table 18. operating modes of the can line interface (continued) input signals output signals act txen tx canh canl v3 mode rtl rth canh canl rx res res res res d7 d0 tm1 tm0 tmux ten
l4969ur-e, L4969URD-E control and status registers doc id 022587 rev 2 31/46 after the xtal driven timer of the microcontroller has calculated the relative cycle time and the corresponding deviation, cg1 and cg0 have to be set to ?10? to disable the adjustment cycle on nint. from the deviation calculated by the microcontroller, the correction factor of the rc-oscillator -15% to 16% can be reprogra mmed with cg1 and cg0 se t to ?00? or ?11?. (?11? can be used to indicate that calibration has already been performed). note, that overwriting this register is only valid, if the cycle measurement was started and terminated properly. this can be tested by evaluating pgen either prior to or during correction (read back via sout). note also, that any write to the wdc register will reset the timer and th us reset t he phase of the testcycle. therefore a cyclic access to the window watchdog during the pulsewidth measurement has to be avoided and the timer watchdog to be used instead (i.e. 1 sec) figure 16. state transition during oscillator calibration 4.5 adr4: wdc watchd og control register figure 17. adr4: wdc wa tchdog control register the startup watchdog is not programmable and will always generate a 1.0 ms low cycle on nreset followed by a 320 ms high cycle unt il an acknowledgment will occur. if no acknowldege is received after the 7th cycle, the device will au tomatically be forced into sleep mode. ?no request? ?2.5ms cycle on nint? ?finish cycle? ?update adj? cg=01 cg=10 cg=00 cg=11 watchdog and interrupt start time measurement at rising edge calculate offset write offset watchdog and interrupt can be enabled has to be disabled swt0 wdt3 swt1 wnd wden wdt2 wdt1 wdt0 d7 d0 wake-up watchdog timing configuration 0000: 80ms 0001: 160ms 0010: 320ms 0011: 640ms 0100: 800ms 1000: 1sec 1001: 2sec 1010: 4sec 1011: 8sec 1100: 45min software window watchdog timing configuration 00: 2.5 - 5ms 01: 5 - 10ms 10: 10 - 20ms 11: 20 - 40ms enable wakeup watchdog, window watchdog will be automatically deactivated until wakeup watchdog expires reserved bits (?res?) have to be written as ?0?. disable window watchdog, only allowed with pgen set, see previous table for osc adjust
control and status registers l4969ur-e, L4969URD-E 32/46 doc id 022587 rev 2 acknowledgment and reset of startup and window watchdog is automatically performed by overwriting (or rewrit ing) this register. note, that with wden set, a cyclic setting of ifr.wkw after the programmed wakeup time will occur. 4.5.1 watchdog configuration figure 18. watchdog configuration note: 1 wr (1) : writing to wdc twice register will restart the timer. rewriting th e wdc register while the wakeup timer just expires can lead to an unwanted window watchdog failure and therefore a low pulse on reset (see note on section 4.5.4). after power-on-reset of v s and v 1 or wakeup from sleep or nreset being forced low externally, the startup watchdog is active, supervising the proper startup of the v 1 supplied microcontroller. upon missing spi write operat ion to the wdc register after 7 reset cycles (1 ms active, 320 ms high) the sleep mode is entered. leaving the forced sleep mode will be automat ically performed upon wakeup via can, an edge on wake or upon device powerup. after successful startup, the window watchdog s upervision is activated, meaning, that the microcontroller has to send an acknowledge within a predefined, programmable window. upon failure, a reset is generated and the startup watchdog is reactivated. if the timer function is requested, the window watchdog is deactivated until expiry of the wakeup time, or rewriting of this register. an y write to this register will reset the timer. startup window wakeup forced sleep wd wd ack ack missing ack timer wr (1) & wden timeout missing ack (after 350ms) extwake can-wake por prog sleep wakeup nreset forced low externally wr & not timeout
l4969ur-e, L4969URD-E control and status registers doc id 022587 rev 2 33/46 4.5.2 startup figure 19. startup after powerup, the l4969ur is expecting the microcontroller to send an acknowledgement within a predefined segmented timing frame of 7 x 320 ms. a missing acknowledgement until after the 2.3s will force the device into sl eep mode until either external or can wakeup or por cause a restart of the sequence above. 4.5.3 window watchdog figure 20. window watchdog after successful acknowledgement of the startup sequence, the window watchdog is automatically activated and cont rolling proper microc ontroller activity by supervising an incoming acknowledge to lie within a predefined programmable window. upon every acknowledge the watchdog is restarting the window. v1 nreset nreset nreset startup acknowledgement via spi within 320ms startup acknowledgement via spi within 640ms no startup acknowledgement via spi within 2.3s (device will enter sleep mode) 1ms early (late) acknowledge supervision 2,5 .. 20ms 5 .. 40ms 50% acknowledge is restarting window early (late) acknowledge supervision
control and status registers l4969ur-e, L4969URD-E 34/46 doc id 022587 rev 2 4.5.4 wakeup watchdog figure 21. wakeup watchdog if the timer is activated during normal mode by setting wden in wdc, an ?acknowledge- free? sequence is started for a predefined pr ogrammable time. window watchdog activity is resumed after expiry of the timer. to be able to detect the timeout, the corresponding interrupt enable must be set in gien. this mode can also be used to allow a bootstrap loader mode with longer execution times than the maximum specified window. correct startup of this loader is safely detected upon missing response following the timeout. note: special considerations for the timer restart via wdc write: due to a restriction in the transition from wake-up watchdog to window watchdog an unwanted low pulse on reset (window watc hdog failure) can be triggered when wdc register is rewritten while the wake-up watchdog just expires. therefore the timer can only be restarted by rewriting wden twice in wdc when the location of the timer expiration is considered. this is the case, when the expiration of th e timer is monitored through timer expiration interrupt via nint (configuration as in figure 21 ). here a safe rewrite to the wdc register is possible directly after this event has been dete cted (the time for event processing plus the duration of the corresponding spi frame are far longer than the wake-up watchdog to window watchdog state transition). when the timer expiration cannot be known while updating the wdc register, two strategies are possible to bypass this behaviour: 1. disable the window watchdog function as described in section 4.5, in the watchdog control register to avoid a false window watchdog failure. the potential impact on a safe application supervision has to be considered. 2. access the internal state of the wake-up watchdog to identify a safe window for a wdc rewrite (see figure 22 ): the internal state of the wake-up watchdog prescaler can be accessed via nint after setting the bit d6, ?cg0? of the rcadj register. to avoid that other active interrupt sources pull nint low they have to be masked by clearing the global interrupt mask register gien. an expiration of the wake-up watchdog can only occur with the rising edge of the rectangular waveform now visible on nint, so that a safe rewrite of the wdc register can take place at any time while nint is high or directly after the falling edge. after wdc rewrite window wd window wd timer (80ms .. 45min) nint ack window & timeout and resume window wd interrupt active upon timeout (via gien) start timer restart timer safely before expiration by writing wdc twice
l4969ur-e, L4969URD-E control and status registers doc id 022587 rev 2 35/46 the bit d6, ?cg0? in rcadj can be cleared again and the original gien value has to be restored. figure 22. valid timing windows for wdc register rewrite. 4.6 adr5: gien global interrupt enable register figure 23. adr5: gien global interrupt enable register critical window for critical window for nint (wdc prescaler wdc rewrite (< 15us) wdc rewrite (< 15us) valid wdc register rewrite 2.5ms 2.5ms after setting cg0 and clearing gien) eovt eew euv ires iset ecw eww eifw d7 d0 enable identifier based wakeup / interrupt enable wakeup,/ interrupt via watchdog enable can wakeup / interrupt enable wakeup / interrupt via edge on wake enable interrupt upon can error recovery enable interrupt upon can error detection enable interrupt upon overtemp. warning enable interrupt upon vs / vreg undervoltage
control and status registers l4969ur-e, L4969URD-E 36/46 doc id 022587 rev 2 4.7 adr6: ifr interrupt flag register figure 24. adr6: ifr in terrupt flag register except espi all bits in this register are ma skable in gien. any masked bit will force nint low until the register content is reset (eithe r explicitly or by spi ?clear register). 4.8 adr7: ctsr can tran sceiver status register figure 25. adr7: ctsr can tr ansceiver stat us register note, that this register, except bit ex, is read only and only provides the unlatched information on current bus errors. bit ex is read only and provides the latched error flag. this bit is reset by forcing the device into normal operation mode (programming act and txen in ctcr). d11 d0 espi iset ires uv23 wkif wkw wkc wke ovt3 ovt2 ovt1 uvvs vs < 7.2v detected overtemperature warning level reached ovt1 : t(v1) > 140degc ovt2 : t(v2) > 140degc ovt3 : t(v3) > 140degc signal edge on wake detected wakeup condition via can detected watchdog timeout detected identifier passed can id-filter reserved bit (?res?) has to be written as ?0?. crc- / format error or sclk- timeout detected by spi (non maskable) can linefailure detected (iset) removed (ires) v2 or v3 undervoltage d11 d0 res res res gsh ei_v eii_ix eiii eiv eviii evii evi ex reserved bits (?res?) are always read as ?0? canh < -1v at falling edge tx tx permanent dominant detected canh permanent dominant detected (txd = ?0?, t > 1.3ms) (canh > 1.8v, t > 1.3ms) short circuit canh to canl detected (canh - canl > -3.25v, t > 1.3ms) canl short circuit to vs detected (canl > 7.2v, t > 32us) canl permanent dominant detected (canl < 3.1v, t > 1.3ms) canh short circuit to vs detected (canh > 7.2v, t > 32us) single wire communication detected (edge count difference > 3) ei_v: canh off eii_ix: canl off
l4969ur-e, L4969URD-E control and status registers doc id 022587 rev 2 37/46 4.9 adr 8 and 9: id01, id23 iden tifier filter sequence select register figure 26. adr 8 and 9: id01 , id23 identifier filter sequence sele ct register identifier of can frame can be divided up into 6 segments numbered from ?a? to ?f?. for each segment a filter register is implemented, enabling different pass functions on every two bit wide block. segments a through c (id01) are located at adr 8 with msb ?c11? segments d through f (id23) are located at adr 9 with msb ?f11? note, that clearing a complete segment disables the whole filter. id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 rtr sega segb segc segd sege segf a00 a01 a10 a11 00 4/2 demux 4/2 demux 11 sof f11 f10 f01 f00 11 00 pass 99at0028 10 01 00 10 01 01 00 01 01 10 00 10 01 11 01 01 01 01 sega segb segc examples: identifiers to pass: sega: a10, a00 0011 0010 id01: 0011 0010 0101 0101 segb: b01 segc: c01, c00 segf: f10, f01 segd: d10, d01 sege: e11, e01, e00 1011 id01: 0110 1011 0110 0011 0110 id bits to be set segf sege segd valid sequence for each segment
control and status registers l4969ur-e, L4969URD-E 38/46 doc id 022587 rev 2 4.10 adr 10: btl identifier filter bittimelogic control register figure 27. adr 10: btl id entifier filter bittim elogic control register the total bitlength equal s the sum of 1 + pseg1 + pseg2 in units of ? s. the location of the sampling point is determined by the length of pseg1. at the start of frame (initial recessive to dominant edge) the bitlength counter is reset. upon every signal edge the counter will be leng thened or shortened acco rding to location of the transition within the programmed boundaries of pseg1 or pseg2. if the edge lies within pseg1 additional cycles are insert ed in order to shift the samp ling point to a safe location after the settling of the input signal. if the signal transition is located within pseg2, this segment will be shortened accordingly with the goal of the next edge to lie at the beginning of pseg1. the amount of cycles one segmen t is lengthened or shortened is determined by the type of edge (rec ? dom or dom ? rec) and the programming of td: the re synchronization jump width will be either set to ?1? (dom ? rec edge) or to 1 + td (rec ? dom edge). note, that the length of one ti me quanta depends on the offset of the on ch ip rc-oscillator and therefore on the accuracy of calibration (see register rcadj (adr 3) for details on frequency correction).
l4969ur-e, L4969URD-E control and status registers doc id 022587 rev 2 39/46 4.11 adr 15: sys system status register figure 28. adr 15: sys sys tem status register the lower 6 bit of this register can be used to analyze the reason of startup (after nreset low). this information is va lid until the first watchdog-acknowledge, and will then be reinitialized to 000001. stf otf wndf stat ncrc ucf wake npor d7 d0 crc-checking disabled warm start after failure of window watchdog reserved status flag (test only) warm start after < 7 missing ack during startup warm start after v1 overtemp failure warm start after 7 missing ack during startup warm start after leaving prog. sleep mode cold start after low vs
interrupt management l4969ur-e, L4969URD-E 40/46 doc id 022587 rev 2 5 interrupt management figure 29. interrupt management all interrupt flags (in ifr) except espi can be masked in the global interrupt enable register (gien). an interrupt will be signalled by nint going low until either the corr esponding mask or the flag itself will be reset by the a pplication software. an autoreset function is available for ifr, allowing to remove all interrupt flags after reading their state (see spi). eovt eew euv ires iset ecw eww eifw d7 d0 d11 d0 espi iset ires uv23 wkif wkw wkc wke ovt3 ovt2 ovt1 uvvs gien ifr nint
l4969ur-e, L4969URD-E remarks for application doc id 022587 rev 2 41/46 6 remarks for application figure 30. general circuit connection diagram note: c * ceramic c close to pin recommended for emi can if
package information l4969ur-e, L4969URD-E 42/46 doc id 022587 rev 2 7 package information 7.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.2 so-20 package information figure 31. so-20 package dimensions ("1($'5
l4969ur-e, L4969URD-E package information doc id 022587 rev 2 43/46 7.3 powerso-20 package information figure 32. powerso-20 package dimensions table 19. so-20 mechanical data symbol millimeters min typ max a 2.35 2.65 a1 0.10 0.30 b 0.33 0.51 c 0.23 0.32 d 12.60 13.00 e 7.40 7.60 e1.27 h 10.0 10.65 h 0.25 0.75 l 0.40 1.27 k0 8 ddd 0.10
package information l4969ur-e, L4969URD-E 44/46 doc id 022587 rev 2 table 20. powerso-20 mechanical data symbol millimeters min typ max a 3.6 a1 0.1 0.3 a2 3.3 a3 0 0.1 b 0.4 0.53 c 0.23 0.32 d 15.8 16 d1 9.4 9.8 e 13.9 14.5 e1.27 e3 11.43 e1 10.9 11.1 e2 2.9 e3 5.8 6.2 g0 0.1 h 15.5 15.9 h 1.1 l0.8 1.1 n8 s 8 t10
l4969ur-e, L4969URD-E revision history doc id 022587 rev 2 45/46 8 revision history table 21. document revision history date revision changes 16-dec-2011 1 initial release. 19-sep-2013 2 updated disclaimer.
l4969ur-e, L4969URD-E 46/46 doc id 022587 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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